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Slow Read Transfers
Slow Read Transfers
When the SLOW_READ parameter is set, CorePCIF transfers read data from the backend interface once every two
clock cycles when RD_SYNC = 0 and once every three clock cycles when RD_SYNC = 1, assuming the Master holds
IRDYN active, as shown in Figure 6-22 and Figure 6-23 on page 72 . If the Master deasserts IRDYN, additional clock
cycles will be inserted between the data transfers. Write transfers operate as normal, and transfers every clock cycle are
supported.
Enabling the SLOW_READ function removes the need for the internal data buffer, and hence reduces the gate count
requirements of the core considerably, especially when the SX-A and RTSX-S families are used.
cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
clk
framen
cben[3:0]
6
0
ad[31:0]
ADDR
0
1
2
3
par
devseln
irdyn
trdyn
dp_start
dp_done
bar_select[2:0]
rd_cyc
rd_stb_out
rd_stb_in
0
mem_add[11:0]
mem_data_in[31:0]
000
0
004
1
008
2
00C
3
010
4
rd_sync
Figure 6-22 · Slow Read Transfer (RD_SYNC = 0)
v4.0
71
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